HP DDR3 DIMMs break through the bandwidth barrier - Reality Check: Server Insights -
HP DDR3 DIMMs break through the bandwidth barrier
By Jeff Fisher.  

If you've figured out the "typical" bandwidth speeds with the new DDR3 memory in all the new Intel-based Nehalem servers, you might recognize performance bandwidth tables like these;

DPC = DIMMs Per Channel

  • 1 DPC = 1333MHz
  • 2 DPC = 1066MHz  <-read below; at hp this is now also 1333MHz!
  • 3 DPC = 800MHz

Originally, only servers that installed one DDR3 DIMM per memory channel could reach speeds of 1333Mhz.  When two DDR3 DIMMS were installed in a memory channel, the fasted memory speeds that could be reached was 1066MHz.

Until now!

HP Engineers have designed an Hewlett-Packard exclusive method so that servers that have two DDR3 DIMMs per memory channel can reach speeds of 1333Mhz!

To add to this HP exclusive, HP just announced an 8GB DDR3 RDIMM that runs at 1333Mhz (previously the fastest 8GB DDR3 RDIMM was 1067MHz).  That new part number is 500662-B21.

So now, you may get the highest capacity DDR3 DIMMs (8GB) at the fast speed available (1333MHz) and populate your server with twice as much memory and still get that fastest speed (1333MHz)!

Of course there are going to be some restrictions, and system performance will vary depending on several factors (Server model, CPU capability, DIMM type and number of DIMM's populated), but this is a cool development.  The new performance is available from a simple ROM update via ROM Based Setup Utility (RBSU).

Check it out; even some of the industry writers have highlighted this: http://blog.scottlowe.org/2009/04/07/hps-proliant-g6-servers/!


Posted 04-28-2009 6:04 PM by s_mathur
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Comments

Mario Martinez wrote re: HP DDR3 DIMMs break through the bandwidth barrier
on 05-26-2009 7:55 PM

Jeff

Very nice write up.  The industry definitely needs something like this to help the DDR3 memory challenges in the system.  In regards to DDR3, can you comment on latency (CL, TAT, CWL) and if the system uses or overrides the latency: spd, cpu register,  MRS, etc.  What have you found on one clock latency on CL and CWL? thanks

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